
chain-address-collision:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400540 <_init>:
  400540:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400544:	910003fd 	mov	x29, sp
  400548:	9400003c 	bl	400638 <call_weak_fn>
  40054c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400550:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400560 <.plt>:
  400560:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400564:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf434>
  400568:	f947fe11 	ldr	x17, [x16, #4088]
  40056c:	913fe210 	add	x16, x16, #0xff8
  400570:	d61f0220 	br	x17
  400574:	d503201f 	nop
  400578:	d503201f 	nop
  40057c:	d503201f 	nop

0000000000400580 <malloc@plt>:
  400580:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400584:	f9400211 	ldr	x17, [x16]
  400588:	91000210 	add	x16, x16, #0x0
  40058c:	d61f0220 	br	x17

0000000000400590 <__libc_start_main@plt>:
  400590:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400594:	f9400611 	ldr	x17, [x16, #8]
  400598:	91002210 	add	x16, x16, #0x8
  40059c:	d61f0220 	br	x17

00000000004005a0 <__gmon_start__@plt>:
  4005a0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005a4:	f9400a11 	ldr	x17, [x16, #16]
  4005a8:	91004210 	add	x16, x16, #0x10
  4005ac:	d61f0220 	br	x17

00000000004005b0 <abort@plt>:
  4005b0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005b4:	f9400e11 	ldr	x17, [x16, #24]
  4005b8:	91006210 	add	x16, x16, #0x18
  4005bc:	d61f0220 	br	x17

00000000004005c0 <puts@plt>:
  4005c0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005c4:	f9401211 	ldr	x17, [x16, #32]
  4005c8:	91008210 	add	x16, x16, #0x20
  4005cc:	d61f0220 	br	x17

00000000004005d0 <__isoc99_scanf@plt>:
  4005d0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005d4:	f9401611 	ldr	x17, [x16, #40]
  4005d8:	9100a210 	add	x16, x16, #0x28
  4005dc:	d61f0220 	br	x17

00000000004005e0 <printf@plt>:
  4005e0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005e4:	f9401a11 	ldr	x17, [x16, #48]
  4005e8:	9100c210 	add	x16, x16, #0x30
  4005ec:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005f0 <_start>:
  4005f0:	d280001d 	mov	x29, #0x0                   	// #0
  4005f4:	d280001e 	mov	x30, #0x0                   	// #0
  4005f8:	aa0003e5 	mov	x5, x0
  4005fc:	f94003e1 	ldr	x1, [sp]
  400600:	910023e2 	add	x2, sp, #0x8
  400604:	910003e6 	mov	x6, sp
  400608:	580000c0 	ldr	x0, 400620 <_start+0x30>
  40060c:	580000e3 	ldr	x3, 400628 <_start+0x38>
  400610:	58000104 	ldr	x4, 400630 <_start+0x40>
  400614:	97ffffdf 	bl	400590 <__libc_start_main@plt>
  400618:	97ffffe6 	bl	4005b0 <abort@plt>
  40061c:	00000000 	.inst	0x00000000 ; undefined
  400620:	0040098c 	.word	0x0040098c
  400624:	00000000 	.word	0x00000000
  400628:	00400a78 	.word	0x00400a78
  40062c:	00000000 	.word	0x00000000
  400630:	00400af8 	.word	0x00400af8
  400634:	00000000 	.word	0x00000000

0000000000400638 <call_weak_fn>:
  400638:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf434>
  40063c:	f947f000 	ldr	x0, [x0, #4064]
  400640:	b4000040 	cbz	x0, 400648 <call_weak_fn+0x10>
  400644:	17ffffd7 	b	4005a0 <__gmon_start__@plt>
  400648:	d65f03c0 	ret
  40064c:	00000000 	.inst	0x00000000 ; undefined

0000000000400650 <deregister_tm_clones>:
  400650:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400654:	91012000 	add	x0, x0, #0x48
  400658:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40065c:	91012021 	add	x1, x1, #0x48
  400660:	eb00003f 	cmp	x1, x0
  400664:	540000a0 	b.eq	400678 <deregister_tm_clones+0x28>  // b.none
  400668:	90000001 	adrp	x1, 400000 <_init-0x540>
  40066c:	f9458c21 	ldr	x1, [x1, #2840]
  400670:	b4000041 	cbz	x1, 400678 <deregister_tm_clones+0x28>
  400674:	d61f0020 	br	x1
  400678:	d65f03c0 	ret
  40067c:	d503201f 	nop

0000000000400680 <register_tm_clones>:
  400680:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400684:	91012000 	add	x0, x0, #0x48
  400688:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40068c:	91012021 	add	x1, x1, #0x48
  400690:	cb000021 	sub	x1, x1, x0
  400694:	9343fc21 	asr	x1, x1, #3
  400698:	8b41fc21 	add	x1, x1, x1, lsr #63
  40069c:	9341fc21 	asr	x1, x1, #1
  4006a0:	b40000a1 	cbz	x1, 4006b4 <register_tm_clones+0x34>
  4006a4:	90000002 	adrp	x2, 400000 <_init-0x540>
  4006a8:	f9459042 	ldr	x2, [x2, #2848]
  4006ac:	b4000042 	cbz	x2, 4006b4 <register_tm_clones+0x34>
  4006b0:	d61f0040 	br	x2
  4006b4:	d65f03c0 	ret

00000000004006b8 <__do_global_dtors_aux>:
  4006b8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	f9000bf3 	str	x19, [sp, #16]
  4006c4:	b0000093 	adrp	x19, 411000 <malloc@GLIBC_2.17>
  4006c8:	39412260 	ldrb	w0, [x19, #72]
  4006cc:	35000080 	cbnz	w0, 4006dc <__do_global_dtors_aux+0x24>
  4006d0:	97ffffe0 	bl	400650 <deregister_tm_clones>
  4006d4:	52800020 	mov	w0, #0x1                   	// #1
  4006d8:	39012260 	strb	w0, [x19, #72]
  4006dc:	f9400bf3 	ldr	x19, [sp, #16]
  4006e0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006e4:	d65f03c0 	ret

00000000004006e8 <frame_dummy>:
  4006e8:	17ffffe6 	b	400680 <register_tm_clones>

00000000004006ec <insert>:
  4006ec:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4006f0:	910003fd 	mov	x29, sp
  4006f4:	f9000fa0 	str	x0, [x29, #24]
  4006f8:	b90017a1 	str	w1, [x29, #20]
  4006fc:	b90013a2 	str	w2, [x29, #16]
  400700:	b94017a0 	ldr	w0, [x29, #20]
  400704:	529d89e1 	mov	w1, #0xec4f                	// #60495
  400708:	72a9d881 	movk	w1, #0x4ec4, lsl #16
  40070c:	9b217c01 	smull	x1, w0, w1
  400710:	d360fc21 	lsr	x1, x1, #32
  400714:	13027c22 	asr	w2, w1, #2
  400718:	131f7c01 	asr	w1, w0, #31
  40071c:	4b010042 	sub	w2, w2, w1
  400720:	528001a1 	mov	w1, #0xd                   	// #13
  400724:	1b017c41 	mul	w1, w2, w1
  400728:	4b010000 	sub	w0, w0, w1
  40072c:	b9002fa0 	str	w0, [x29, #44]
  400730:	d2800200 	mov	x0, #0x10                  	// #16
  400734:	97ffff93 	bl	400580 <malloc@plt>
  400738:	f90013a0 	str	x0, [x29, #32]
  40073c:	f94013a0 	ldr	x0, [x29, #32]
  400740:	b94017a1 	ldr	w1, [x29, #20]
  400744:	b9000001 	str	w1, [x0]
  400748:	b9802fa0 	ldrsw	x0, [x29, #44]
  40074c:	d37df000 	lsl	x0, x0, #3
  400750:	f9400fa1 	ldr	x1, [x29, #24]
  400754:	8b000020 	add	x0, x1, x0
  400758:	f9400001 	ldr	x1, [x0]
  40075c:	f94013a0 	ldr	x0, [x29, #32]
  400760:	f9000401 	str	x1, [x0, #8]
  400764:	b9802fa0 	ldrsw	x0, [x29, #44]
  400768:	d37df000 	lsl	x0, x0, #3
  40076c:	f9400fa1 	ldr	x1, [x29, #24]
  400770:	8b000020 	add	x0, x1, x0
  400774:	f94013a1 	ldr	x1, [x29, #32]
  400778:	f9000001 	str	x1, [x0]
  40077c:	d503201f 	nop
  400780:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400784:	d65f03c0 	ret

0000000000400788 <creat_hash>:
  400788:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40078c:	910003fd 	mov	x29, sp
  400790:	f90017a0 	str	x0, [x29, #40]
  400794:	f90013a1 	str	x1, [x29, #32]
  400798:	b9001fa2 	str	w2, [x29, #28]
  40079c:	b9003fbf 	str	wzr, [x29, #60]
  4007a0:	1400000d 	b	4007d4 <creat_hash+0x4c>
  4007a4:	b9803fa0 	ldrsw	x0, [x29, #60]
  4007a8:	d37ef400 	lsl	x0, x0, #2
  4007ac:	f94013a1 	ldr	x1, [x29, #32]
  4007b0:	8b000020 	add	x0, x1, x0
  4007b4:	b9400000 	ldr	w0, [x0]
  4007b8:	b9401fa2 	ldr	w2, [x29, #28]
  4007bc:	2a0003e1 	mov	w1, w0
  4007c0:	f94017a0 	ldr	x0, [x29, #40]
  4007c4:	97ffffca 	bl	4006ec <insert>
  4007c8:	b9403fa0 	ldr	w0, [x29, #60]
  4007cc:	11000400 	add	w0, w0, #0x1
  4007d0:	b9003fa0 	str	w0, [x29, #60]
  4007d4:	b9403fa1 	ldr	w1, [x29, #60]
  4007d8:	b9401fa0 	ldr	w0, [x29, #28]
  4007dc:	6b00003f 	cmp	w1, w0
  4007e0:	54fffe2b 	b.lt	4007a4 <creat_hash+0x1c>  // b.tstop
  4007e4:	d503201f 	nop
  4007e8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4007ec:	d65f03c0 	ret

00000000004007f0 <search>:
  4007f0:	d100c3ff 	sub	sp, sp, #0x30
  4007f4:	f9000fe0 	str	x0, [sp, #24]
  4007f8:	b90017e1 	str	w1, [sp, #20]
  4007fc:	f90007e2 	str	x2, [sp, #8]
  400800:	52800020 	mov	w0, #0x1                   	// #1
  400804:	b90027e0 	str	w0, [sp, #36]
  400808:	b94017e0 	ldr	w0, [sp, #20]
  40080c:	529d89e1 	mov	w1, #0xec4f                	// #60495
  400810:	72a9d881 	movk	w1, #0x4ec4, lsl #16
  400814:	9b217c01 	smull	x1, w0, w1
  400818:	d360fc21 	lsr	x1, x1, #32
  40081c:	13027c22 	asr	w2, w1, #2
  400820:	131f7c01 	asr	w1, w0, #31
  400824:	4b010042 	sub	w2, w2, w1
  400828:	528001a1 	mov	w1, #0xd                   	// #13
  40082c:	1b017c41 	mul	w1, w2, w1
  400830:	4b010000 	sub	w0, w0, w1
  400834:	b90023e0 	str	w0, [sp, #32]
  400838:	b98023e0 	ldrsw	x0, [sp, #32]
  40083c:	d37df000 	lsl	x0, x0, #3
  400840:	f9400fe1 	ldr	x1, [sp, #24]
  400844:	8b000020 	add	x0, x1, x0
  400848:	f9400000 	ldr	x0, [x0]
  40084c:	f90017e0 	str	x0, [sp, #40]
  400850:	f94007e0 	ldr	x0, [sp, #8]
  400854:	b900001f 	str	wzr, [x0]
  400858:	1400000a 	b	400880 <search+0x90>
  40085c:	f94017e0 	ldr	x0, [sp, #40]
  400860:	f9400400 	ldr	x0, [x0, #8]
  400864:	f90017e0 	str	x0, [sp, #40]
  400868:	b94027e0 	ldr	w0, [sp, #36]
  40086c:	11000400 	add	w0, w0, #0x1
  400870:	b90027e0 	str	w0, [sp, #36]
  400874:	f94007e0 	ldr	x0, [sp, #8]
  400878:	b94027e1 	ldr	w1, [sp, #36]
  40087c:	b9000001 	str	w1, [x0]
  400880:	f94017e0 	ldr	x0, [sp, #40]
  400884:	f100001f 	cmp	x0, #0x0
  400888:	540000c0 	b.eq	4008a0 <search+0xb0>  // b.none
  40088c:	f94017e0 	ldr	x0, [sp, #40]
  400890:	b9400000 	ldr	w0, [x0]
  400894:	b94017e1 	ldr	w1, [sp, #20]
  400898:	6b00003f 	cmp	w1, w0
  40089c:	54fffe01 	b.ne	40085c <search+0x6c>  // b.any
  4008a0:	f94017e0 	ldr	x0, [sp, #40]
  4008a4:	f100001f 	cmp	x0, #0x0
  4008a8:	54000060 	b.eq	4008b4 <search+0xc4>  // b.none
  4008ac:	b94023e0 	ldr	w0, [sp, #32]
  4008b0:	14000002 	b	4008b8 <search+0xc8>
  4008b4:	12800000 	mov	w0, #0xffffffff            	// #-1
  4008b8:	9100c3ff 	add	sp, sp, #0x30
  4008bc:	d65f03c0 	ret

00000000004008c0 <display>:
  4008c0:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008c4:	910003fd 	mov	x29, sp
  4008c8:	f9000fa0 	str	x0, [x29, #24]
  4008cc:	b9002fbf 	str	wzr, [x29, #44]
  4008d0:	14000018 	b	400930 <display+0x70>
  4008d4:	b9802fa0 	ldrsw	x0, [x29, #44]
  4008d8:	d37df000 	lsl	x0, x0, #3
  4008dc:	f9400fa1 	ldr	x1, [x29, #24]
  4008e0:	8b000020 	add	x0, x1, x0
  4008e4:	f9400000 	ldr	x0, [x0]
  4008e8:	f100001f 	cmp	x0, #0x0
  4008ec:	540000a1 	b.ne	400900 <display+0x40>  // b.any
  4008f0:	90000000 	adrp	x0, 400000 <_init-0x540>
  4008f4:	912ca000 	add	x0, x0, #0xb28
  4008f8:	97ffff3a 	bl	4005e0 <printf@plt>
  4008fc:	1400000a 	b	400924 <display+0x64>
  400900:	b9802fa0 	ldrsw	x0, [x29, #44]
  400904:	d37df000 	lsl	x0, x0, #3
  400908:	f9400fa1 	ldr	x1, [x29, #24]
  40090c:	8b000020 	add	x0, x1, x0
  400910:	f9400000 	ldr	x0, [x0]
  400914:	b9400001 	ldr	w1, [x0]
  400918:	90000000 	adrp	x0, 400000 <_init-0x540>
  40091c:	912cc000 	add	x0, x0, #0xb30
  400920:	97ffff30 	bl	4005e0 <printf@plt>
  400924:	b9402fa0 	ldr	w0, [x29, #44]
  400928:	11000400 	add	w0, w0, #0x1
  40092c:	b9002fa0 	str	w0, [x29, #44]
  400930:	b9402fa0 	ldr	w0, [x29, #44]
  400934:	7100741f 	cmp	w0, #0x1d
  400938:	54fffced 	b.le	4008d4 <display+0x14>
  40093c:	f9400fa0 	ldr	x0, [x29, #24]
  400940:	9100a000 	add	x0, x0, #0x28
  400944:	f9400000 	ldr	x0, [x0]
  400948:	f9400400 	ldr	x0, [x0, #8]
  40094c:	b9400001 	ldr	w1, [x0]
  400950:	90000000 	adrp	x0, 400000 <_init-0x540>
  400954:	912ce000 	add	x0, x0, #0xb38
  400958:	97ffff22 	bl	4005e0 <printf@plt>
  40095c:	f9400fa0 	ldr	x0, [x29, #24]
  400960:	9100a000 	add	x0, x0, #0x28
  400964:	f9400000 	ldr	x0, [x0]
  400968:	f9400400 	ldr	x0, [x0, #8]
  40096c:	f9400400 	ldr	x0, [x0, #8]
  400970:	b9400001 	ldr	w1, [x0]
  400974:	90000000 	adrp	x0, 400000 <_init-0x540>
  400978:	912d0000 	add	x0, x0, #0xb40
  40097c:	97ffff19 	bl	4005e0 <printf@plt>
  400980:	d503201f 	nop
  400984:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400988:	d65f03c0 	ret

000000000040098c <main>:
  40098c:	a9ac7bfd 	stp	x29, x30, [sp, #-320]!
  400990:	910003fd 	mov	x29, sp
  400994:	90000000 	adrp	x0, 400000 <_init-0x540>
  400998:	912ea001 	add	x1, x0, #0xba8
  40099c:	910083a0 	add	x0, x29, #0x20
  4009a0:	a9400c22 	ldp	x2, x3, [x1]
  4009a4:	a9000c02 	stp	x2, x3, [x0]
  4009a8:	a9410c22 	ldp	x2, x3, [x1, #16]
  4009ac:	a9010c02 	stp	x2, x3, [x0, #16]
  4009b0:	b9402021 	ldr	w1, [x1, #32]
  4009b4:	b9002001 	str	w1, [x0, #32]
  4009b8:	b9013fbf 	str	wzr, [x29, #316]
  4009bc:	14000008 	b	4009dc <main+0x50>
  4009c0:	b9813fa0 	ldrsw	x0, [x29, #316]
  4009c4:	d37df000 	lsl	x0, x0, #3
  4009c8:	910123a1 	add	x1, x29, #0x48
  4009cc:	f820683f 	str	xzr, [x1, x0]
  4009d0:	b9413fa0 	ldr	w0, [x29, #316]
  4009d4:	11000400 	add	w0, w0, #0x1
  4009d8:	b9013fa0 	str	w0, [x29, #316]
  4009dc:	b9413fa0 	ldr	w0, [x29, #316]
  4009e0:	7100741f 	cmp	w0, #0x1d
  4009e4:	54fffeed 	b.le	4009c0 <main+0x34>
  4009e8:	910083a1 	add	x1, x29, #0x20
  4009ec:	910123a0 	add	x0, x29, #0x48
  4009f0:	52800122 	mov	w2, #0x9                   	// #9
  4009f4:	97ffff65 	bl	400788 <creat_hash>
  4009f8:	910123a0 	add	x0, x29, #0x48
  4009fc:	97ffffb1 	bl	4008c0 <display>
  400a00:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a04:	912d2000 	add	x0, x0, #0xb48
  400a08:	97fffef6 	bl	4005e0 <printf@plt>
  400a0c:	910073a1 	add	x1, x29, #0x1c
  400a10:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a14:	912d6000 	add	x0, x0, #0xb58
  400a18:	97fffeee 	bl	4005d0 <__isoc99_scanf@plt>
  400a1c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400a20:	b9013ba0 	str	w0, [x29, #312]
  400a24:	b9401fa1 	ldr	w1, [x29, #28]
  400a28:	910063a2 	add	x2, x29, #0x18
  400a2c:	910123a0 	add	x0, x29, #0x48
  400a30:	97ffff70 	bl	4007f0 <search>
  400a34:	b9013ba0 	str	w0, [x29, #312]
  400a38:	b9413ba0 	ldr	w0, [x29, #312]
  400a3c:	3100041f 	cmn	w0, #0x1
  400a40:	54000100 	b.eq	400a60 <main+0xd4>  // b.none
  400a44:	b9401ba1 	ldr	w1, [x29, #24]
  400a48:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a4c:	912d8000 	add	x0, x0, #0xb60
  400a50:	2a0103e2 	mov	w2, w1
  400a54:	b9413ba1 	ldr	w1, [x29, #312]
  400a58:	97fffee2 	bl	4005e0 <printf@plt>
  400a5c:	14000004 	b	400a6c <main+0xe0>
  400a60:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a64:	912e6000 	add	x0, x0, #0xb98
  400a68:	97fffed6 	bl	4005c0 <puts@plt>
  400a6c:	52800000 	mov	w0, #0x0                   	// #0
  400a70:	a8d47bfd 	ldp	x29, x30, [sp], #320
  400a74:	d65f03c0 	ret

0000000000400a78 <__libc_csu_init>:
  400a78:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a7c:	910003fd 	mov	x29, sp
  400a80:	a901d7f4 	stp	x20, x21, [sp, #24]
  400a84:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf434>
  400a88:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf434>
  400a8c:	91374294 	add	x20, x20, #0xdd0
  400a90:	913722b5 	add	x21, x21, #0xdc8
  400a94:	a902dff6 	stp	x22, x23, [sp, #40]
  400a98:	cb150294 	sub	x20, x20, x21
  400a9c:	f9001ff8 	str	x24, [sp, #56]
  400aa0:	2a0003f6 	mov	w22, w0
  400aa4:	aa0103f7 	mov	x23, x1
  400aa8:	9343fe94 	asr	x20, x20, #3
  400aac:	aa0203f8 	mov	x24, x2
  400ab0:	97fffea4 	bl	400540 <_init>
  400ab4:	b4000194 	cbz	x20, 400ae4 <__libc_csu_init+0x6c>
  400ab8:	f9000bb3 	str	x19, [x29, #16]
  400abc:	d2800013 	mov	x19, #0x0                   	// #0
  400ac0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400ac4:	aa1803e2 	mov	x2, x24
  400ac8:	aa1703e1 	mov	x1, x23
  400acc:	2a1603e0 	mov	w0, w22
  400ad0:	91000673 	add	x19, x19, #0x1
  400ad4:	d63f0060 	blr	x3
  400ad8:	eb13029f 	cmp	x20, x19
  400adc:	54ffff21 	b.ne	400ac0 <__libc_csu_init+0x48>  // b.any
  400ae0:	f9400bb3 	ldr	x19, [x29, #16]
  400ae4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400ae8:	a942dff6 	ldp	x22, x23, [sp, #40]
  400aec:	f9401ff8 	ldr	x24, [sp, #56]
  400af0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400af4:	d65f03c0 	ret

0000000000400af8 <__libc_csu_fini>:
  400af8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400afc <_fini>:
  400afc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400b00:	910003fd 	mov	x29, sp
  400b04:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400b08:	d65f03c0 	ret
